(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of integrating salicide and self-aligned contact processes using a unique layout method in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, logic products are often produced using salicide (self-aligned silicide) processes in order to obtain higher circuit performance. In silicidation, a refractory metal layer is deposited and then annealed. The underlying silicon reacts with the refractory metal layer to produce a silicide overlying the gate electrode and source and drain regions. The silicided gate and source/drain regions have lower resistance than non-silicided regions, especially in smaller geometries, and hence, higher circuit performance.
In the production of memory units, the self-aligned contact (SAC) has been widely used to reduce cell size, thus greatly increasing the device density for the CMOS product design. With the advent of Large Scale Integration (LSI) many of the integrated circuits formed on semiconductor substrates comprise several circuit functions on a single chip. For example, memory devices are formed on the same chip as the logic circuits which address them. It is desired to find a method of integrating the salicide and the SAC processes on one wafer so that both high logic performance and high density memory for embedded memory can be achieved.
The standard SAC process needs to use an insulator-capped polysilicon. This makes the process incompatible with the salicide process. Co-pending U.S. patent application Ser. No. 09/298,933 to Weining et al, filed on Apr. 26, 1999, provided a method for integrating salicide and self-aligned contact processes in the fabrication of logic circuits with embedded memory by using an additional poly-cap masking layer. But the traditional approach for this process will require very tight process control for the small poly-cap space in order to achieve small RAM cell size. This limitation greatly increases the process difficulties and cost.
Silicidation has been widely used in the art. Silicidation techniques and self-aligned contacts are discussed in Silicon Processing for the VLSI Era, Vol. 2, by S. Wolf, Lattice Press, Sunset Beach, Calif., c. 1990, pp. 144-149 and in ULSI Technology, by C. Y. Chang and S. M. Sze, McGraw-Hill, New York, N.Y., c. 1996, pp.397-402 and 487-488. U.S. Pat. No. 5,573,980 to Yoo shows a method of forming a salicided SAC for an SRAM, but with no embedded logic. U.S. Pat. Nos. 5,605,853 and 5,719,079, both to Yoo et al teach formation of a 4T SRAM and floating gate memory and logic device including salicide and a butted contact, but not including a SAC.
Accordingly, it is a primary object of the present invention to provide an effective and very manufacturable method for integrating salicide and self-aligned contact processes in the fabrication of integrated circuits.
It is a further object of the invention to provide a process for integrating salicide and self-aligned contact processes in the fabrication of logic circuits with embedded memory.
Yet another object is to form salicided gate and source/drain regions in the logic circuits of an integrated circuit device while also forming self-aligned contacts in the memory circuits of the same integrated circuit device.
Yet another object of the invention is to form salicided gate and source/drain regions in the logic circuits of an integrated circuit device while also forming self-aligned contacts in the memory circuits of the same integrated circuit device using a special layout technique.
A still further object of the invention is to provide a method for integrating salicide and self-aligned contact processes by using a poly cap mask and a special layout technique to achieve cell size reduction while avoiding process difficulties.
In accordance with the objects of the invention, a method for integrating salicide and self-aligned contact processes in the fabrication of integrated circuits by using a poly cap mask and a special layout technique is achieved. A pair of gate electrodes and associated source and drain regions are formed overlying a semiconductor substrate wherein nitride spacers are formed on sidewalls of the gate electrodes. A poly-cap layer is deposited overlying the gate electrodes and source and drain regions. The poly-cap layer is selectively removed overlying one of the source and drain regions between the gate electrode pair where a self-aligned contact is to be formed and removed over one of the gate electrode pair. An insulating layer is deposited over the surface of the semiconductor substrate. The planned self-aligned contact opening is made through the insulating layer wherein the contact opening touches the adjacent gate electrode of the pair. The self-aligned contact opening is filled with a conducting layer to complete fabrication of the integrated circuit device.